1. Field of the Invention
This invention relates to electronic circuits and, more particularly, to current sense amplifier circuits used in semiconductor devices.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Many modern semiconductor memories employ differential bit lines and some sort of differential amplifier or sensing circuit in their design. These differential amplifiers and sense circuits are commonly known as sense amplifiers (or “sense amps”). In addition to memory devices, sense amplifiers may be used in programmable arrays and many other applications. A wide variety of sense amps are known in the art, including current sensing and voltage sensing variations.
For example, dynamic random access memory (DRAM) devices usually employ voltage sense amplifiers (VSAs) for detecting the state of a DRAM memory cell. In voltage sensing, the bitline is precharged before the memory cell is activated. When the memory cell is activated, the memory cell charges or discharges the bitline to maintain or change the voltage of the bitline. However, the bitline may be quite long in some memory devices (e.g., large memory arrays), resulting in a large capacitive load for the memory cell. In some cases, the memory cell may not be able to provide enough cell current to quickly discharge or charge a large bitline, and an excessive amount of time may be needed to read the memory cells. Therefore, voltage sensing may not be the preferred sensing scheme in some memory devices (e.g., when operation speed is of concern).
For this reason, current sense amplifiers (ISAs) are widely used to measure signals in memory devices. Current sense amplifiers are well suited to measuring signals on heavily loaded capacitive lines, such as those found in memory devices or programmable array devices, where it would be slow to measure voltage. Located in a sense amplifier (SA) cell, the current sense amplifier measures a current and turns this into a small voltage difference output. In some cases, the output of a current sense amplifier may be passed to a voltage sense amplifier (VSA) also located in the sense amplifier cell, which amplifies the low voltage signal to a higher voltage signal. The output of the voltage sense amplifier may then be passed as the output of the sense amplifier cell.
FIG. 1 illustrates one embodiment of a current sense amplifier (ISA), which is located within a sense amp (SA) cell 150 for detecting a current differential between the complementary bitlines of a memory array (such as memory array 100). Once detected, the current differential is converted into a small voltage differential by ISA 130 and then supplied to voltage sense amplifier (VSA) 140, where it is amplified and output from the sense amp cell. In the embodiment shown, ISA 130 is coupled for receiving a pair of differential currents (IBL,IBLB) from one or more complementary bitlines (BL, BLB) of memory array 100. In some cases, ISA 130 may be coupled for receiving the pair of differential currents from only one column of memory cells (e.g., column 0 via COLMUX 110). In other cases, ISA 130 may be coupled for receiving the pair of differential currents from more than one column of memory cells (e.g., columns 0-N via COLMUX 110 to 120). The column multiplexers (COLMUX) are generally used to switch between the pairs of bitlines, depending on the column of memory cells selected.
FIG. 2 shows a conventional current sense amplifier design 200 with cross-coupled PMOS transistors (M1,M2), PMOS load transistors (M3,M4) and NMOS enable transistor (M8). When employed within a memory device, differential bitline currents (IBL,IBLB) may be supplied to the source terminals of cross-coupled transistors M1 and M2 during a read operation. To be “cross-coupled,” the gate terminal of PMOS transistor M1 must be coupled to the drain terminal of PMOS transistor M2, and vice versa. The drain terminals of cross-coupled transistors M1 and M2 may then be coupled to ground through load transistors M3, M4 and enable transistor M8. In this manner, ISA 200 may be configured for converting the pair of differential currents into a pair of differential voltages during times in which the sense amplifier is enabled (e.g., when an active enable signal is supplied to transistor M8). In some cases, the pair of differential voltages may be supplied to a voltage sense amplifier (not shown). If used, the VSA may amplify the differential voltages and use the amplified voltages to generate a single-ended sense amplifier output voltage.
In the circuit of FIG. 2, the memory cell current flows into the low impedance source nodes of the cross-coupled PMOS transistors (M1, M2), where the current is translated into voltage. The input impedance looking into the source nodes of transistors M1, M2 may be approximately equal to:
                              r                      i            ⁢                                                  ⁢            n                          =                              1            -                                          r                                                      o                    ⁢                    _                    ⁢                    M                    ⁢                    3                                    /                  4                                            ⁢                              gm                                  M                  ⁢                                                                          ⁢                                      1                    /                    2                                                                                            gm                          M              ⁢                                                          ⁢                              1                /                2                                                                        EQ        .                                  ⁢        1            where ro—M3/4 is the output impedance of transistors M3, M4 and gmM1/2 is the transconductance of transistors M1, M2. In most cases, transistors M1, M2 and M3, M4 are carefully sized to make ro—M3/4gmM1/2 as close to one as possible so that the input impedance will be approximately equal to zero. A low input impedance usually enables the sense amp to detect the differential currents as soon as possible and to generate an output voltage as high as possible.
However, the conventional circuit shown in FIG. 2 has a number of disadvantages. First of all, even though transistors M1, M2 and M3, M4 are carefully sized, random process variations may prevent the transistor pairs from having identical characteristics. In one example, process variations may cause the threshold voltage of transistor M1 to be somewhat higher than the threshold voltage of transistor M2, or vice versa. In another example, process variation may cause the transconductance or saturation current to differ between devices M1 and M2. However, transistors M1 and M2 are not the only devices to suffer from mismatch—transistors M3/M4 and devices in the memory cell may suffer, as well. In some cases, transistor mismatch may cause the sense amplifier to detect the wrong voltage at the beginning of a sense cycle. For example, the differential currents initially supplied to the current sense amplifier may be relatively weak. During this time (i.e., at the start of a sense cycle), transistor mismatch may cause more current to flow in one leg of the sense amp than the other, thereby causing the sense amplifier output to “go in the wrong direction” until the differential currents are firmly established.
Another disadvantage of the conventional circuit of FIG. 2 is that the optimal size of the PMOS load transistors (M3 and M4) is a strong function of VCC for speed and stability. As such, it is often difficult to achieve high performance across a wide range of power supply voltages (VCC) with the same load. In addition to speed and stability concerns, the circuit performance tends to suffer (or even fail) at lower power supply voltages (e.g., about 1.2V and lower).
Therefore, it would be desirable to provide a current sense amplifier solution that remedies the disadvantages of conventional solutions. For example, an improved current sense amplifier would exhibit an improvement in mismatch tolerance, operational speed and stability over a wide range of power supply voltages, including power supply voltages lower than about 1.2V.